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Cache Coherence & the MESI protocol

Two cores, each with its own cache, sharing one variable x in RAM. Click the buttons and watch each cache's MESI state change. The key moment: when one core writes, the other core's copy is invalidated — it goes stale and must be re-fetched.

Main memory (RAM): x = 0

Core 1

L1 cache line for x

—

I Invalid

Core 2

L1 cache line for x

—

I Invalid

M — Modified E — Exclusive S — Shared I — Invalid

Try this sequence: Core 1 reads (→ E) · Core 2 reads (→ both S) · Core 1 writes (→ Core 1 M, Core 2 I) · Core 2 reads (a coherence miss: Core 1 writes back, then both go S).